1. Field of the Invention
The present invention relates to a semiconductor memory having a dynamic memory cell which needs refresh operation, and a method for operating the semiconductor memory.
2. Description of the Related Art
In recent years, a semiconductor memory called a pseudo-SRAM has received attention. The pseudo-SRAM, which has memory cells (dynamic memory cells) of a DRAM, operates as an SRAM by automatically carrying out refresh operation of the memory cells inside thereof. The dynamic memory cell is small in size, so that it is possible to develop the pseudo-SRAM with low cost per bit and high capacity.
The pseudo-SRAM generates an internal refresh request for carrying out the refresh operation irrespective of (asynchronously with) an external access request (a read request or a write request). Thus, there are cases where the refresh operation conflicts with access operation (read operation or write operation). Since the pseudo-SRAM has an SRAM interface, it is necessary to hide the refresh operation from an external system even when a conflict occurs. Accordingly, in this type of pseudo-SRAM, an external access cycle (product specification) is set longer than the sum total of actual time of the single access operation (internal access operation time) carried out inside the pseudo-SRAM in response to the external access request, and actual time of the single refresh operation (refresh operation time) carried out inside the pseudo-SRAM. The external access cycle refers to a minimum supply interval of the external access request. In the read operation, read access time, which refers to time from receiving the read request until outputting read data, becomes longest, when the read request conflicts with the internal refresh request and the read operation is carried out after the refresh operation.
A semiconductor memory such as the pseudo-SRAM has redundancy circuits in order to relieve a defect, which is caused by crystal defect in a substrate, particles during a fabrication process, and the like, and to improve a yield. To be more specific, in a test process, for example, a redundancy word line is used instead of a defected word line to relieve the defect. In the pseudo-SRAM having the redundancy circuits, the presence or absence of the use of the redundancy circuits has to be judged on an access operation basis and a refresh operation basis. Thus, time for a redundancy judgement causes increase in the access time. Especially, when the read request conflicts with the internal refresh request and the read operation is carried out after the refresh operation, it is necessary to carry out the redundancy judgement twice from receiving the read request until outputting the read data. Therefore, there is much effect on the access time.
The semiconductor memory such as the pseudo-SRAM has a refresh counter which successively generates refresh addresses indicating the memory cells to be refreshed. A technology for carrying out the redundancy judgement of the next refresh address in advance, by using the fact that the refresh addresses are successively generated, is disclosed. (For example, Japanese Unexamined Patent Application Publication Nos. 2003-323798 and 2003-68071)
In the read operation, a read address is supplied to the pseudo-SRAM with the read request. Thus, it is impossible to carry out the redundancy judgement of the read address in advance before receiving the read request, in contrast to that of the refresh address. Therefore, the redundancy judgement of the read address is conventionally carried out after the refresh operation, when the read request conflicts with the internal refresh request and the read operation is performed after the refresh operation.